ESD protection circuit is a component commonly found in almost every semiconductor chip. The ESD protection circuit protects a semiconductor chip from damages caused by transient voltages or currents. Transient voltages or currents brought by accumulated charges of certain materials can easily release charges due to friction. Therefore, ESD protection circuits are invented and positioned closely to pads in the chips. When excessive transient voltages or currents occur, ESD protection circuits can respond in time and direct the excessive transient voltages or currents into the power rails to avoid those voltages or currents from flowing to the core circuits.
There are three main categories of ESD modes which are MM (Machine Mode), HBM (Human Body Mode) and CDM (Charge Device Mode) depending on where the accumulated charges come from. The MM mode is used to simulate the manufacturing environment and there are several specifications designated for the MM mode. The HBM mode is used to simulate the static charges caused by human bodies when people touch the pins of semiconductor chips with their hands. Those charges will flow through the pins and cause damages to the semiconductor chips. The CDM mode is the most undesirable mode for chips with large chip areas. The static charges of the CDM mode are charges accumulated inside the body of a chip during the manufacturing processes and will discharge to the outside environment regardless of whether the environment has static charges or not. Thus, since static charges may exist anywhere an effective ESD protection becomes ever more important.
The simplest ESD protection circuit comprises of two reverse biased diodes, one formed between the power source and an input pad, and the other between the ground and the input pad. Both reverse biased diodes are turned off when the chip is operating under normal conditions. A normal power supplier often provides voltages that does not exceed fifty volts. The reverse biased diode turns into break down mode when the voltage on the input pad exceeds the break down voltage of the reverse biased diode. A diode under break down mode can bypass and shunt the current quickly. A diode also sustains more ESD stress than other circuit components, e.g., MOS (Metal Oxidation Semiconductor) devices or BJT (Bipolar Junction Transistor) devices.
U.S. Pat. No. 6,297,536 to Yu, entitled “Diode structure compatible with silicide processes for ESD protection,” discloses a diode structure having a diffusion region where the whole edge is encompassed by N-well to increase the ballistic resistance of the diode under high current stressing conditions. The disclosure of this patent is hereby incorporated by reference. The diode structure also has a silicide layer covering the diffusion region such that a discharge current can flow through the silicide layer and the diffusion region uniformly because the silicide layer provides better conductive property. An ESD protection circuit utilizing a diode structure as a discharging tool has the advantages of simplicity and small area, but it can not respond to large transient voltages or currents in a short time. It can delay the response time for large transient voltages or currents which require a large junction area to pass through because larger area creates larger parasitic capacitance. If the parasitic capacitor is too large, the protection mechanism of the ESD diode may not be able to react with those discharging events. Therefore, several ESD protection circuits may employ active circuit components, e.g., parasitic bipolar junction transistors, to actively and effectively discharge transient voltages or currents.
U.S. Pat. No. 6,492,859 to Vashchenko et al., entitled “Adjustable electrostatic discharge protection clamp,” discloses an ESD protection circuit for an analog bipolar circuit. The disclosure of this patent is hereby incorporated by reference. The ESD protection circuit in the prior art uses a reverse-coupled NPN BJT acting as an avalanche diode which has a breakdown voltage adjustable by a resistor between the base and collector of the BJT. The reverse-coupled NPN BJT forces another PNP BJT into conduction such that the base current of the PNP BJT is multiplied by the reverse-coupled NPN BJT. The resistor is connected to the reverse-coupled transistor to adjust the breakdown voltage of the reverse-coupled transistor. Effectively, the resistor is used to reduce the breakdown voltage of the reverse-coupled transistor. Although an adjustable resistor is used in this disclosure, the invention does not show any compact layout pattern associated with the disclosed circuit.
In FIG. 1, it shows layout patterns of an ESD protection circuit for high voltage application according to a conventional design. A layout pattern 11 of the ESD protection circuit on a P type substrate has an N type heavily doped region 2, an N type lightly doped region 3, a P type heavily doped region 6 and a P type lightly doped region 5. The N type lightly doped region 3 forms a PN junction diode with the P type substrate that couples with a P type heavily doped region 4. The P type lightly doped region 5 also forms a PN junction diode with an additional N type WELL region 1 encompassing an N type heavily doped region 8, the P type heavily doped region 6 and the P type lightly doped region 5. The N type WELL region 1 is an N type doped region functioned as a substrate of P type semiconductor devices. The ESD protection circuit generally has two PN junction diodes wherein the diodes are formed by two parasitic bipolar junction transistors with appropriate electrical connections. Generally, a simple electrical configuration can be a metal wire connected to an I/O pad to the N type heavily doped region 2 and the P type heavily doped region 6 with the P type heavily doped region 4 connected to the ground and the N type heavily doped region 8 connected to the power.
The layout pattern of the ESD protection circuit in FIG. 1 forms the conventional ESD protection circuit comprising two reverse biased diodes, one formed between the power source and an input, and the other between the ground and the input pad.